The present invention generally relates to the testing of Integrated Circuits (ICs). More specifically, the present invention relates to methods and systems for optimizing a test plan for testing ICs.
ICs must be tested for their functionality and their compliance to required specifications. The total test time of an IC depends on a number of factors. Firstly, it is affected by the time required by the functional elements within the IC to settle into a particular mode of operation. The total test time is also affected by the time required to configure test-voltage supplies, relay matrices, signal generators, measurement instruments, and the like. Moreover, the total test time includes the time taken to transfer test data between the IC and a host computer through a communication medium such as a communication bus or a General Purpose Interface Bus (GPIB). Repetitive measurements of various parameters of the IC, such as voltage, current, frequency, RF power, noise, etc., also contribute to the total test time.
Test software used to test ICs use delays during the execution of a test plan. Delays are used to account for the time taken (hereinafter referred to as the desired wait time) by the measurement instrument to stabilize, the time taken to configure different test parameters and components, and the like. For example, a test plan may require a voltage source to change its output voltage to a specified voltage level. Once the test plan triggers the voltage source to change the voltage, the voltage source takes a certain amount of time to stabilize at the specified voltage level. A reliable measurement of a parameter may not be possible until the voltage source settles down at the specified voltage level. Hence, a test plan developer usually inserts a delay in the test plan, to account for the stabilizing time of the voltage source.
In another example, a delay may be required to account for the time needed by a measurement instrument to stabilize after the measurement range of the measurement instrument is changed. In yet another example, a delay may be required for functional elements within the IC to settle down. For example, the test plan may instruct a Phase Locked Loop (PLL) within an IC, to change a frequency of an internal Voltage Controlled Oscillator (VCO). Accordingly, a delay needs to be introduced, to account for the time taken by the PLL to stabilize the VCO to the required frequency.
The total test time of an IC is largely affected by the delay timings used in the test plan. For example, a test plan of an IC may require an RF measurement to be performed on one of its pins. An RF measurement instrument, used to perform the RF measurement, may take a definite amount of time to stabilize before it can perform a reliable measurement on the pin. Therefore, the test plan includes a delay of a time period equal to the stabilizing time required by the RF measurement instrument. The instruction in the test plan, corresponding to performing the RF measurement, is executed only after the time period corresponding to the delay has elapsed.
During the delay, no other activity is performed. A large number of delays, introduced in testing, may therefore result in an increase in the total test time of the IC. Further, when a plurality of ICs is being tested in a test assembly, the total test time of the plurality of ICs may increase significantly. An increase in the total test time directly affects the cost of the IC, as the total test time of the IC is directly related to its cost.
In light of the foregoing discussion, there is a need for efficiently utilizing delay timings in a test plan for an IC, to reduce the total test time. Moreover, there is a need for an optimized test plan that is capable of reducing the overall test time of a plurality of ICs.